{"product_id":"advanced-asic-chip-synthesis-using-synopsysr-design-compilertm-and-primetimer-paperback","title":"Advanced ASIC Chip Synthesis: Using Synopsys(r) Design Compiler(tm) and Primetime(r) - Paperback","description":"\u003cdiv\u003e\u003cp style=\"text-align: right;\"\u003e\u003ca href=\"https:\/\/reportcopyrightinfringement.com\/\" target=\"_blank\" rel=\"nofollow\"\u003e\u003cb\u003eReport copyright infringement\u003c\/b\u003e\u003c\/a\u003e\u003c\/p\u003e\u003c\/div\u003e\u003cp\u003eby \u003cb\u003eHimanshu Bhatnagar\u003c\/b\u003e (Author)\u003c\/p\u003e\u003cp\u003e\u003cem\u003eAdvanced ASIC Chip Synthesis: Using Synopsys(R) Design\u003c\/em\u003e \u003cem\u003eCompiler(R) and PrimeTime(R)\u003c\/em\u003e describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. \u003cbr\u003e The emphasis of this book is on real-time application of Synopsys tools used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-arounds described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solutions. \u003cbr\u003e \u003cem\u003eAdvanced ASIC Chip Synthesis: Using Synopsys(R) Design\u003c\/em\u003e \u003cem\u003eCompiler(R) and PrimeTime(R)\u003c\/em\u003e is intended for anyone who is involved in the ASIC design methodology, starting from RTL synthesis to final tape-out. Target audiences for this book are practicing ASIC design engineers and graduate students undertaking advanced courses in ASIC chip design and DFT techniques. \u003cbr\u003e From the Foreword: \u003cbr\u003e  This book, written by Himanshu Bhatnagar, provides a comprehensive overview of the ASIC design flow targeted for VDSM technologies using the Synopsis suite of tools. It emphasizes the practical issues faced by the semiconductor design engineer in terms of synthesis and the integration of front-end and back-end tools. Traditional design methodologies are challenged and unique solutions are offered to help define the next generation of ASIC design flows. The author provides numerous practical examples derived from real-world situations that will prove valuable to practicing ASIC design engineers as well as to students of advanced VLSI courses in ASIC design'. \u003cbr\u003e Dr Dwight W. Decker, Chairman and CEO, Conexant Systems, Inc., (Formerly, Rockwell Semiconductor Systems), Newport Beach, CA, USA.\u003c\/p\u003e\n            \u003cdiv\u003e\n\u003cstrong\u003eNumber of Pages:\u003c\/strong\u003e 284\u003c\/div\u003e\n            \u003cdiv\u003e\n\u003cstrong\u003eDimensions:\u003c\/strong\u003e 0.66 x 9.21 x 6.14 IN\u003c\/div\u003e\n            \u003cdiv\u003e\n\u003cstrong\u003ePublication Date:\u003c\/strong\u003e October 23, 2012\u003c\/div\u003e\n            ","brand":"BooksCloud","offers":[{"title":"Default Title","offer_id":47438180122845,"sku":"9781461346623","price":96.21,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0811\/9867\/8237\/files\/NHRIcXV4ZUFHd1p4cC9wcGloUkRtdz09.webp?v=1771417132","url":"https:\/\/handfulofbooks.com\/products\/advanced-asic-chip-synthesis-using-synopsysr-design-compilertm-and-primetimer-paperback","provider":"Handful of Books","version":"1.0","type":"link"}